／HDL設計驗證工具／HES－硬體加速平台

HES－硬體加速平台
＜產品簡介＞
HES是一個單一的硬體加速平台，它能夠讓模擬的效能達到最高極限，並且以10到50倍的速度加快ASIC 和FPGA的設計驗證速度。此單一方案讓許多不同的設計及驗證元件，在一個緊密的系統下運作，能夠有效地提升速度及效率。
HES is a unified hardware acceleration solution that maximizes simulation performance and accelerates ASIC and FPGA design verification by 10x-50x over traditional methods. The unified solution provides greater speed and efficiency by bringing together many different design and verification elements in one seamless system.

＜功能特色＞
■HES元件包含: 設計驗證管理軟體、高效能的模擬器 、和硬體加速板
■驗證模式Verification modes
■可與ARM 作業系統協同模擬Co-verification of ARM Systems
■SystemC/Acceleration board co-simulation
■嵌入式記憶體Embedded Memories
■除錯功能Debugging
■Assertions
■ASIC to FPGA Clock Conversion
■Incremental Synthesis
■C-Models Overview
■Automatic Design Partitioning in the Simulation Mode
■VHDL Testbench Conversion to C++